Designing
Embedded Systems with PIC Microcontrollers - Principles & Practice
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Notes:
All information on building the Derbot AGV appears in the Derbot
site section.
Errata (except for tiny typos) appear in chapter sections.
Select the chapter you want to go to.
| Chapter 1 | Chapter 7 | Chapter 13 | Chapter 19 |
| Chapter 2 | Chapter 8 | Chapter 14 | Chapter 20 |
| Chapter 3 | Chapter 9 | Chapter 15 | Appendix 2 |
| Chapter 4 | Chapter 10 | Chapter 16 | Appendix 3 |
| Chapter 5 | Chapter 11 | Chapter 17 | Appendix 5 |
| Chapter 6 | Chapter 12 | Chapter 18 | Book CD |
Chapter 3
Errata
Page 60, 4th line, the last word should read "crystal", not "capacitor".
While Fig. 1.3 shows a picture of the pingpong circuit made using a pcb, it can also be constructed on stripboard, for example as shown here (click on image to expand). A more compact component distribution is also possible. Find instructions to make this version here.
Programming Exercise 5.7
It is intended that this runs with the original Fibonacci program, i.e.
Program Example 5.6. If run with the version of Program Example 5.7 a stopwatch
value of 226us is reported.
A Note on Case Sensitivity in MPLAB
From Program Example 5.7 the book starts using Include Files, described on
Page 106. From this point case sensitivity in MPLAB must be disabled, as the
Include File uses symbols written in upper case, while the book programs are
written in lower case. Access case sensitivity (in MPLAB ver. 7.22) by clicking
Project -> Build Options -> Project ->MPASM Assembler (or Project
-> Build Options -> project name). An example of
Assembler errors if this is not done is seen in
Development Tools: Frequently Asked Questions.
A Note on Trace Displays
Figure 5.9 in the book shows an MPLAB Version 7.20 screen print. It has the line
numbers running from 0 to +142, where the breakpoint occurs.
More recent versions of MPLAB have the line numbers counting up from a negative number, to line 0, where the breakpoint occurs. Both versions display from top to bottom. The difference is that one ends on line 0, while the other starts there!
Another difference is that the Trace display in Version 7.20 treats all branches as single line instructions, while later versions gives them two lines each. It's as if this version is actually showing the flow of instructions in the pipeline. Thus every branch instruction is accompanied by a NOP. Therefore, for the same Trace operation, there are more lines in a Version 7.4 Trace, compared to a Version 7.20 one.
The equivalent screen image for Figure 5.9, using Version 7.22, is shown below. Notice the NOP in line -5 which follows the GOTO instruction. The total number of lines in this Trace is 165. If you count all of these NOPs, and subtract that from 165, you get to the 142 lines of Figure 5.9. Interestingly, the number of cycles is the same in each print, except that the book print does not indicate that the final GOTO instruction will take 2 cycles.
Errata
Page 92: the explanation relating btfsc and btfss in the
second to last paragraph is reversed.
Page 96: first line last paragraph, should read "The simple delay loop
of Program Example 5.2...."
Page 108: Program Example 5.9, last two lines should read:
bfbclr
porta,4,wait ;go to wait if right paddle pressed
bfbclr porta,3,wait ;go to wait if left paddle pressed
(i.e. bfbclr macro used on both lines)
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Chapter 6
Errata
Page 126, Simulation Exercise 6.1:
The
reset state of the INTEDG bit and its effect is described "up side down"
in this exercise. The
reset state of the INTEDG bit is logic 1. The relevant sentences can be
rewritten:
... Now “fire” the RB0 pin, setting RB0 high, and an interrupt sequence should be instigated as you single step further. See the Hardware Stack change, program execution transfer to the ISR, and on ISR completion the program resuming after the instruction where it was interrupted. Fire the RB0 pin again (returning it to 0), and continue stepping. This will cause no change to program execution, as the interrupt edge response will be positive-edge triggered only (the INTEDG bit has been left at Reset value of 1). Try changing the INTEDG bit (to 0), as shown in the program....
Page 139: the last paragraph should reference Fig. 2.11, not Fig. 2.10.
Errata
The last two lines should read:
· the architecture of the 16F87XA family, of which the 16F873A is a member,
· the 16F87XA memory map and interrupt structure,
Program Example 9.7 was written for the SRF04 ultrasonic ranger. If used with a SRF05 sensor, then it doesn't work, as there is a longer time delay between pulse input, and echo pulse output. The data sheet indicates 700us, though measurements have returned higher values (approaching 800us). Therefore the 300us delay introduced in the program is inadequate. A simple program change is to remove the 300us delay, and insert these two lines, causing a wait until the echo pulse goes high:
btfss portc,6 ;wait until echo pulse goes high
goto $-1
The later lines
;add in blanked 3cms (this derived
experimentally)
addlw 3
can also be removed or the added value adjusted.
Errata
The key to Fig. 10.28 references
bits RCIF, RCIE twice. The correct reference is: For RCIF, RCIE, see Fig.
7.12.
Errata
The first
sentences of page 313 should read:
The input multiplexer, seen to the right of the diagram, has 5 channels for the
16F873A and ’F876A, and 8 for 16F874A and ’F877A. The inputs are shared with
five of the six Port A bits, and three of the eight Port E (for 16F874 and
’F877) bits.
The last sentence in the second to
last paragraph of page 313 should read:
Best practice is therefore to set the ADC clock frequency such that it has a
period equal to or just more than 1.6ms.
Program Example 9.7 is referenced on page 329 of this chapter. Check comments about it under Chapter 9.
Section 19.8 is a very brief consideration of the issue of RTOS overheads. It is worth noting that the comments made apply primarily to small-scale programs, such as the ones we have considered in the book. For larger programs, it may be that these simple generalisations do not apply, i.e. that an RTOS-based program is inevitably longer than its sequentially-programmed equivalent. For example, for a program of 10-12 tasks, the code length may be actually shorter than its equivalent, written as a super-loop.
Appendix 3
Errata
Fig. A3.1: There are two R10's and two R17's in this diagram. A revised
circuit diagram is available on the Derbot
page.
Fig. A3.2: A pull-up resistor of value 1kW should be
shown, connected from pin 6 of the 16F873A to +5V.
Errata
Program Example 8.4
There is a small error in this program. In the
initialisation an attempt is made to write to the PR2 SFR, with the bank select
bits incorrectly set. This appears in the program section:
bcf status,rp0 ;select bank 0
;set up PWM
…
movlw D'249' ;sets
PWM period. (alternative values can be used)
movwf
pr2
The result of this is that the number D'249' is written to the T2CON register, which occupies the same location as PR2, in bank 0. This overwrites the setting previously placed in T2CON. In this case, D'249' = B'1111 1001. Checking the layout of T2CON (Fig 9.5 in book), we can see that, with bit 2 being 0, this turns Timer 2 off, and the PWM no longer functions.
To fix, set bit rp0 to 1 before writing to PR2! The simplest way to do this is to move that write up to where the TRIS registers are being accessed; these lie in Bank 1. The code section then appears:
bcf status,rp1
bsf status,rp0 ;select memory bank 1
movlw
B'00000000' ;set port A bits according to their function, 1=input, 0=output
movwf
trisa
…
movlw D'249' ;sets
PWM period. (alternative values can be used)
movwf
pr2
bcf status,rp0 ;select bank 0
;set up PWM
Etc
Program Example 8.7
The Delay1 subroutine was written for an 8MHz clock, but applied here with a
4MHz clock, without adjustment. In this program the delay introduced is not
critical, so this error is not significant. The subroutine should be corrected
if it is to be used in a context which is time critical. A correct version
can be seen in other programs, e.g.
Program Example 9.7.
Program Example 9.7
The I2C_send_stop subroutine has mysteriously
lost its last two lines, although these appear in other programs which use this
subroutine. Fortunately the effect is minimal, as program execution
proceeds on to the next subroutine, a short delay, and the program appears to
right itself. The subroutine, as shown here in full, should of course be
corrected if the program is to be used.
I2C_send_stop bsf status,rp0
bsf sspcon2,pen
;force stop bit.
btfss sspstat,p
;test for stop bit completion
goto $-1
bcf status,rp0
return
Program Example 11.3
Unfortunately the version for a slightly earlier Derbot has crept in. A
change of two bits in the TRISB setting is required, as shown:
;Initialise
...
movlw B'00110000'
movwf trisb
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